The self-aligned silicidation of the source and drain contacts used in silicon metal-oxide semiconductor field effect transistors (MOSFET) technology consumes a significant portion of the layer of the substrate silicon and forms a relatively rough interface with the underlying silicon. This roughness of the silicide/silicon interface along with the significant consumption of the silicon layer can adversely affect the structure of the transistor in the vicinity of the formed silicide drain and source contacts in both bulk silicon and silicon-on-insulator (SOI) transistors. In the case of a shallow junction (less than 200 nanometers), in bulk or SOI process, the encroachment of the contact silicide into the depletion region of the junction can cause excessive leakage currents. In the case of very thin SOI, the silicidation of the contact regions can lead to full consumption of the silicon film under the contact and a separation between the contact and the channel of the transistor.
To avoid these problems, thinner silicide contact regions may be used. However, this adversely compromises the resistivity of the silicide contact layer.
In devices having very shallow junctions and/or ultra thin silicon-on-insulator layers, less than 50 nanometers thick, the use of thinner silicides ceases to be a valid alternative.
One solution to this problem, as taught by S. S. Wong et al. in their article "Elevated Source/Drain MOSFET", published in the IEDM TECHNICAL DIGEST 634 (1984) and by M. Rodder et al. in their article "Raised Source/Drain MOSFET With Dual Sidewall Spacers", published in the IEEE ELECTRON DEVICE LETTER, 12(3), 89 (1991) is to thicken the silicon source and drain contact areas by selective chemical vapor deposition (CVD) silicon epitaxial growth after the formation of the poly-silicon gate and side wall spacers, and prior to the deposition of a refractory metal on these contact regions for the subsequent formation of the silicide contacts. FIGS. 1A, 1B and 1C show the processing steps disclosed by the prior art to thicken the source and drain contact regions prior to depositing the refractory metal over the drain and source contact regions.
FIG. 1 shows the structure of a field effect transistor on an SOI substrate prior to thickening the source and drain regions. As shown, the SOI substrate consists of an oxide layer 12 formed on a substrate 10, and a crystalline silicon layer 14 less than 200 nanometers thick formed on the silicon oxide layer 12. In the alternative, a bulk silicon substrate may be used in place of the SOI substrate which eliminates both the oxide layer 12 and the silicon layer 14. In the bulk case, subsequent references to the silicon layer 14 will imply the entire silicon substrate. A polysilicon gate 16 is formed on a thin gate oxide layer (not shown) on the silicon layer 14. A silicon nitride layer 18 is formed on top of the polysilicon gate 16, and a silicon dioxide (SiO.sub.2) side wall spacer 20 is formed on the sides of gate 16. The silicon side wall spacer 20 circumscribes the polysilicon gate 16.
The thickness of the silicon layer 14 in the source contact region 24 and the drain contact region 26 is increased by 100 to 300 nanometers by selective chemical vapor deposition (CVD) epitaxially grown silicon layer 28 as shown in FIG. 1B.
The epitaxially grown silicon layer 28 grows faceted leaving V-shaped grooves 32 and 34 outside of the side wall spacer 20. During the formation of the silicide contacts, the silicide is likely to penetrate into the silicon layer 14 at the bottom of the grooves 32 and 34 toward the underlying source and drain junction. In the case of a thin silicon layer of a silicon-on-insulator substrate, the formation of the silicide could erode or consume the silicon layer 14 completely. To prevent the deposition of the refractory metal, used to form the silicide, on the bottoms of the V grooves 32 and 34, the prior art process requires the formation of a second side wall 36 to mask the V grooves as shown in FIG. 1C.
The second side wall 36 prevents the silicide contacts subsequently formed on the source and drain contact regions from penetrating the junction in the silicon layer 14 in a bulk silicon process, and from fully consuming a part of the silicon layer 14 adjacent to the bottom of the V groove in the case of a silicon-on-insulator (SOI) process.
The invention is a method for increasing the thickness of the source and drain contact regions which replaces the selectively grown silicon epitaxial layers with solid phase epitaxial regrowth of a deposited amorphous layer.